Asymmetric pulse train generator having means for reversing the asymmetrical characteristic



Nov. 25, 1969 G. E. MAS 3,480,798

ASYMMETRIG PULSE TRAIN GENERATOR HAVING MEANS FOR REVERSING THE ASYMMETRICAL CHARACTERISTIC Filed July 12, 1966 2 Sheets-Sheet 2 COMMON COUNTER INVENTOR. GEORGE E Mas ATTORNEY United States Patent 3,480,798 ASYMMETRIC PULSE TRAIN GENERATOR HAVING MEANS FOR REVERSING THE ASYMMETRICAL CHARACTERISTIC George E. Mas, West Hempsted, N.Y., assignor to Sperry Rand Corporation, a corporation of Delaware Filed July 12, 1966, Ser. No. 564,610 Int. Cl. H031: 5/20; G01c 19/00 U.S. Cl. 307-260 6 Claims ABSTRACT OF THE DISCLOSURE An asymmetric pulse train generator in which first and second pulses are algebraically combined on alternate cycles for providing an asymmetric pulse train having alternate pulses representative of the first pulse width and of the first pulse width algebraically combined with the second pulse width that includes means for periodically reversing the asymmetrical characteristic of the asymmetric pulse train.

The present invention relates to an asymmetric pulse train generator having means for reversing the asymmetrical characteristic.

It has been found in gyroscopic apparatus that undesirable gyroscopic drift can be reduced by rotating the intermediate races of each of two diametrically opposed compound bearings of the support mechanism in opposite directions and reversing the direction of rotation of each of the intermediate races periodically as disclosed in U.S. Patent No. 2,970,480 entitled Anti-Friction Support Mechanism for Gyroscopic Devices of Zeigler et al., issued Feb. 7, 1961 and assigned to the same assignee as the present invention. Further improvement in the averaging of the undesirable torques thereby reducing the drift characteristic can be achieved as disclosed in U.S. patent application S.N. 473,984, now Patent No. 3,365,959, entitled Anti-Friction Support Mechanisms for Gyroscopic Devices of T. R. Quermann, filed July 22, 1965 by asym metrically driving the intermediate races in order that each bearing is driven further in one direction than the other such that the ball complement has a definite progression. Then the direction of asymmetry is periodically reversed to cancel the average bias torque created by the asymmetry.

The present invention provides self-contained apparatus for generating an asymmetric pulse train having an asymmetric reversing characteristic suitable for use with the apparatus of said U.S. patent application S.N. 473,984. An advantage of the present invention is that it is completely selfcontained and generates the desired asymmetric pulse train when supplied only with a conventional DC. power source. In addition, it is readily compensated and adjusted to provide an accurate asymmetric characteristic and if desired, may be easily varied to provide a different asymmetric characteristic. Further, the complete circuit of the present invention can be packaged in a relatively small module by means of microcircuits.

It is a primary object of the present invention to provide an asymmetric pulse train generator having means for reversing asymmetry.

It is another object of the present invention to provide a self-contained asymmetric pulse train generator having means for reversing asymmetry.

It is an additional object of the present invention to provide an asymmetric pulse train generator having means for reversing asymmetry in which the asymmetric characteristics may be varied easily and accurately.

These and other objects of the present invention will become apparent by referring to the drawings in which:

3,480,798 Patented Nov. 25, 1969 FIGS. la and b are electrical schematic diagrams showing an asymmetric pulse train generating apparatus having means for reversing asymmetry in accordance with the present invention; and

FIG. 2 is a graph showing representative waveforms of the circuit of FIGS. 1a and b and their interrelationships.

Referring now to FIGS. la and b, a main pulse generator 10 has a unijunction transistor 11 responsive to an RC timing circuit 12 comprising a resistor R and a capacitor C The pulse generator 10 is connected through an isolation gate 13 to a bistable flip-flop 14. The output of the flip-flop 14 is connected to a dual gating circuit 15 which comprises gates 16 and 17. The output of the flip-flop 14 is also connected through a counter driver 20 to a counter 21. In addition, the output of the flip-flop 14 is connected to a dual gating circuit 22 which is further responsive to the motor carrier frequency indicated by the legend, for reasons to be explained.

One state of the output of the counter 21 is connected to the gate circuit 16 while the other state of the counter 21 is connected to the gate circuit 17. The outputs of the gate circuits 16 and 17 are connected to :an input terminal of a bistable flip-flop 23 which has its output terminals connected through a gate circuit 24 to a. delay pulse generator 25. The delay pulse generator 25 includes a unijunction transistor 26 responsive to the output of an RC timing circuit 27 comprising a resistor R and a capacitor C The output of the pulse generator 25 is connected through an isolation gate 28 to reset the flip-flop 23. The output of the flip-flop 23 is also connected to an inhibit gate 29 which in turn is connected to control the main pulse generator 10.

Although the apparatus of the present invention may start in any binary state, it will be assumed for purposes of explanation that the following conditions prevail initially as shown in FIGS. 1a and b. The binary state of the output of the gate 13 is 1, the state of the flip-flop 14 is as shown, the output of gate 16 is 1, the state of the flipflop 23 is as shown, the output of gate 24 is 0, the output of the counter 21 is as shown, the gate 17 is inhibited by the output of the counter 21, and the output of the gate 28 is 1.

In operation, at t=0 as shown in the waveforms of FIG. 2, the capacitor C of the main pulse generator 10 starts to charge until the firing point of the unijunction transistor 11 is attained. At that time the capacitor C discharges through the transistor 11 to ground resulting in a positive-going pulse which changes the state of the flipflop 14 via gate 13. This defines the leading edge of the first pulse having a duration P of the output waveform E The output of the fiip-flop 14 drives through the gate 16 to change the state of the flip-flop 23. This results in a dual action. The pulse generator 10 is inhibited by the gate 29 and the capacitor C of the delay pulse generator 25 starts to charge via gate 24. When the capacitor C charges to the firing point of the unijunction transistor 26, the capacitor C discharges to ground through the transistor 26 resulting in a positive output pulse. This pulse through the gate 28 resets the flip-flop 23 thereby permitting the main pulse generator 10 to start to generate another main pulse while simultaneously inhibiting the pulse generator 25. This results in a pulse having a duration of P -l-P where the delay is equal to P A second main pulse is generated when the voltage across the capacitor C again reaches the firing point of the unijunction transistor 11. However, at this time, no delay pulse is generated because the flip-flop 14 is in the opposite state to that which it was at t=0. Therefore, the pulse generator 10 recycles producing a third main pulse as shown in FIG. 2. Now, however, the flip-flop 14 is now in its original state and a delay pulse is again generated.

As shown in FIG. 2, the basic period P of the output waveform E depends upon the time constant determined by the resistor R and the capacitor C while the period of the delay P depends upon the time constant established by the resistor R and the capacitor C The resistors and capacitors R C and R C may be made variable as shown in FIGS. 1a and b to vary the respective time constants and thus the pulse widths and asymmetrical characteristics of the pulse train, if desired.

The one and zero state of the pulse train of the output waveform E continues with alternate pulse widths of P and P -j-P respectively, until the output of the counter 21 changes state which, for example in this case, may be after eight cycles. At that time, the gate 16 is inhibited and the gate 17 functions thereby resulting in the one state of the output waveform E having a duration or period equal to F i-P i.e., the basic pulse duration plus the delay and the zero state being equal to P This condition continues until the output of counter 21 again changes state.

An important feature of the present invention is that at the time of change of the state of the counter 21, the output waveform E is symmetrical, i.e., the adjacent pulse duration at the end of one eight cycle period and the beginning of the next eight cycle period are equal, either two half cycles each having a duration of P or two half cycles each having a duration of P +P are adjacent. Thus, if at one change, the two P half cycles are adjacent; at the next change, the two P +P half cycles will be adjacent. This is a unique requirement of the drive required of the motor which drives the compound support bearings of the gyroscope as explained more fully in said U.S. patent application S.N. 473,984.

The number of asymmetrical half cycles of either polarity depends upon the design of the counter 21 and the gates 16 and 17. As will be appreciated, any number of asymmetrical half cycles may be generated and the changeover may be made asymmetrically if so desired. The asymmetry between adjacent asymmetrical pulses depends on the period or time constant of the pulse generator 25 and therefore any desired degree of asymmetry may be provided.

The output waveform E appears on leads 30 and 31 from the flip-flop 14. The basic pulse duration, for example, may be 5.2840 seconds with a delay every other pulse of .133 sec. resulting in asymmetrical pulse train having the characteristics shown in FIG. 2 where the binary one state for example represents clockwise rotation of the motor driving the compound bearings and the binary zero state represents counterclockwise rotation.

The output waveform E is connected on leads 30 and 31 to the input of the dual gate 22 which is also responsive to the motor carrier frequency. The dual gate 22 serves to couple the motor carrier frequency and to couple between the asymmetric pulse train generator of the present invention and the motor drive amplifier, for example, as shown in US. patent application S.N. 363,425, now Patent No. 3,336,810, of M. A. Schaffer entitled Anti- Friction Support Means for Gyroscopes, filed Apr. 28, 1964, to drive a motor to provide the desired asymmetric bearing cycle as explained in said US. patent application S.N. 473,494.

While the invention has been described in its preferred embodiments, it is to be understood that the words which have been used are words of description rather than limitation and that changes within the purview of the appended claims may be made Without departing from the true scope and spirit of the invention in its broader aspects.

What is claimed is:

1. An asymmetric pulse train generator having means for reversing asymmetry comprising (a) first pulse generating means for providing first pulses having a first predetermined pulse width,

(b) second pulse generating means for providing second pulses having a second predetermined pulse width,

(c) means responsive to said first and second pulses for elfectively algebraically combining said first and second pulses on alternate cycles for providing an asymmetric pulse train having alternate pulses representative of said first pulse width and of said first pulse width algebraically combined with said second pulse width, and

(d) means responsive to said asymmetric pulse train for periodically reversing the asymmetrical characteristic of said asymmetric pulse train.

2. An asymmetric pulse train generator of the character recited in claim 1 in which said first pulse generating means includes an oscillator having a unijunction transistor responsive to an RC timing circuit and cooperative with a flip-flop circut in which the time constant of said RC circuit and the firing point of said unijunction transistor in combination with the action of said flip-flop circuit determines said first pulse width.

3. An asymmetric pulse train generator of the character recited in claim 1 in which said second pulse generating means includes an oscillator having a unijunction transistor responsive to an RC timing circuit and cooperative with a flip-flop circuit in which the time constant of said RC circuit and the firing point of said unijunction transistor in combination with the action of said flip-flop circuit determines said second pulse width.

4. An asymmetric pulse train generator of the character recited in claim 1 in which said combining means includes gating means for rendering said second pulses eifective on alternate half cycles.

5. An asymmetric pulse train generator of the character recited in claim 1 in which said reversing means includes counting means responsive to said asymmetric pulse train for periodically reversing the asymmetrical characteristic of said asymmetric pulse train after a predetermined number of cycles thereof.

6. An asymmetric pulse train generator of the character recited in claim 5 in which said reversing means includes counting means and gating means responsive to said asymmetric pulse train for periodically reversing the asymmetrical characteristic of said asymmetric pulse train after a predetermined number of cycles thereof, in which said gating means renders the last pulse of a preceding count and the first pulse of the succeeding count identical.

References Cited UNITED STATES PATENTS 2,645,713 7/1953 Pritchard 328- XR 3,007,115 10/1961 Batley 328-195 XR 3,125,730 3/1964 Levy et al. 307265 XR 3,226,568 12/1965 Samwel 307293 XR 3,268,820 8/1966 Newman et al. 307293 XR 3,388,346 6/1968 Roof et al. 307293 XR DONALD D. FORRER, Primary Examiner STANLEY D. MILLER, Assistant Examiner US. Cl. X.R. 

